In recent years, development of a ferroelectric memory (FeRAM) retaining information in a ferroelectric capacitor by making use of a polarization inversion of a ferroelectric substance has been in progress. The ferroelectric memory is a nonvolatile memory in which retained information does not disappear even when power is turned off, and a high integration, a high-speed driving, a high durability, and a low power consumption can be realized.
As a material of a ferroelectric film constituting the ferroelectric capacitor, a ferroelectric oxide having a perovskite crystal structure such as PZT (Pb (Zr, Ti) O3), SBT (SrBi2Ta2O9) whose amount of remanent polarization is large has been mainly used. The amount of remanent polarization of PZT is approximately 10 μC/cm2 to 30 μC/cm2. However, characteristics of the ferroelectric film are likely to be deteriorated by moisture penetrating from outside through an interlayer insulating film, such as a silicon oxide film, having high affinity with water. That is, in performing a high temperature process such as forming the interlayer insulating film or metal wirings, the moisture is decomposed to hydrogen and oxygen, and this hydrogen penetrates into the ferroelectric film to react with oxygen constituting the ferroelectric film, resulting that oxygen deficiency in the ferroelectric film is caused. As a result, crystallinity of the ferroelectric film is lowered.
Further, using the ferroelectric memory for a long time also causes crystallinity to be lowered due to the penetration of hydrogen into the ferroelectric film. As a result, the amount of remanent polarization and a dielectric constant of the ferroelectric film are lowered, and therefore, performance of the ferroelectric capacitor is lowered. There is also a case that performance of not only the ferroelectric capacitor but also a transistor and the like positioned therebelow is lowered.
Thus, in a conventional ferroelectric memory, in order to suppress diffusion of moisture and hydrogen, an aluminum oxide film is formed on various locations. There are, for example, a ferroelectric memory in which an aluminum oxide film covering a ferroelectric capacitor is formed, a ferroelectric memory in which an aluminum oxide film is formed above wirings, a ferroelectric memory in which a flat aluminum oxide film is formed above a ferroelectric capacitor, and so on.
Here, a conventional manufacturing method of a ferroelectric memory will be explained. FIG. 9A to FIG. 9M are cross-sectional views showing a conventional manufacturing method of a ferroelectric memory in order of steps.
First, as illustrated in FIG. 9A, an element isolation insulating film 102 is formed on a surface of a semiconductor substrate 101 composed of silicon or the like. Next, an ion implantation of B (boron) is performed in the surface of an element region demarcated by the element isolation insulating film 102 thereby forming a P-well 103. Next, gate insulating films 104 and gate electrodes 105 are formed on the P-well 103. Thereafter, an ion implantation of P (phosphorus) is performed in the surface of the P-well 103 thereby forming shallow impurity diffusion layers 106. Subsequently, sidewall insulating films 107 are formed on lateral sides of the gate electrodes 105. Next, an ion implantation of As (arsenic) is performed in the surface of the P-well 103 thereby forming deep impurity diffusion layers 108. Thus, transistors Tr are formed. Note that the single transistor Tr includes the two impurity diffusion layers 108, and one of them is shared with another transistor Tr. The impurity diffusion layer 108 that is shared constitutes a drain, and the impurity diffusion layer 108 that is not shared constitutes a source.
Next, as illustrated in FIG. 9B, a silicon oxynitride film 111 covering the transistors Tr is formed, and an NSG film 112 is formed thereon with using TEOS. Next, a surface of the NSG film 112 is flattened.
Thereafter, as illustrated in FIG. 9C, a resist pattern 191 having openings at positions matching with the impurity diffusion layers 108 is formed on the NSG film 112. Then, etching of the NSG film 112 and so on is performed with using the resist pattern 191 as a mask thereby forming contact holes 113s reaching the sources and a contact hole 113d reaching the drain.
Subsequently, as illustrated in FIG. 9D, the resist pattern 191 is removed. Next, a barrier metal film (not-illustrated) is formed on the entire surface, and a tungsten film (not-illustrated) is formed thereon. Then, the tungsten film and the barrier metal film are polished until the NSG film 112 is exposed. As a result, contact plugs 114s are formed in the contact holes 113s, and a contact plug 114d is formed in the contact hole 113d. Next, plasma annealing is performed in a nitrogen atmosphere, and thereby the surface of the NSG film 112 is nitrided. Thereafter, a silicon oxynitride film 115 is formed on the NSG film 112.
Subsequently, as illustrated in FIG. 9E, an NSG film 116 is formed on the silicon oxynitride film 115 with using TEOS, and then a dehydration treatment thereof is performed. Next, an aluminum oxide film 117 is formed on the NSG film 116 and then a heat treatment (RTA) is performed.
Next, as illustrated in FIG. 9F, a platinum film 118, a PZT film 119, and an iridium oxide film 120 are formed sequentially on the aluminum oxide film 117. A heat treatment (RTA) is performed between forming the PZT film 119 and forming the iridium oxide film 120. Further, the iridium oxide film 120 has a two-layer structure, and a heat treatment (RTA) is also performed after the lower layer is formed.
Thereafter, as illustrated in FIG. 9G, the iridium oxide film 120 is patterned, and then recovery annealing is performed. Subsequently, the PZT film 119 is patterned, and then recovery annealing is performed. Next, an aluminum oxide film 121 is formed on the entire surface, and then recovery annealing is performed.
Subsequently, as illustrated in FIG. 9H, the aluminum oxide film 121 and the platinum film 118 are patterned. Thus, ferroelectric capacitors C are formed. Thereafter, recovery annealing is performed. Further, an aluminum oxide film 122 is formed on the entire surface, and then recovery annealing is performed. Subsequently, an NSG film 123 is formed on the aluminum oxide film 122 with using TEOS, and then the surface thereof is flattened.
Next, plasma annealing is performed in a nitrogen atmosphere, and thereby the surface of the NSG film 123 is nitrided. Next, as illustrated in FIG. 9I, an NSG film 124 is formed on the NSG film 123 with using TEOS, and then plasma annealing is performed in a nitrogen atmosphere, so that the surface of the NSG film 124 is nitrided. Thereafter, an aluminum oxide film 125 is formed on the entire surface. Subsequently, an NSG film 126 is formed on the aluminum oxide film 125 with using TEOS, and then plasma annealing is performed in a nitrogen atmosphere, so that the surface of the NSG film 126 is nitrided.
Next, as illustrated in FIG. 9J, a resist pattern 192 having openings at predetermined positions is formed on the NSG film 126. Then, etching of the NSG film 126 and so on is performed with using the resist pattern 192 as a mask thereby forming contact holes 127t reaching top electrodes (the iridium oxide film 120) and contact holes 127b reaching bottom electrodes (the platinum film 118).
Next, as illustrated in FIG. 9K, the resist pattern 192 is removed, and then recovery annealing is performed. Thereafter, a resist pattern 193 having openings at predetermined positions is formed on the NSG film 126. Then, etching of the NSG film 126 and so on is performed with using the resist pattern 193 as a mask thereby forming contact holes 128s reaching the contact plugs 114s and a contact hole 128d reaching the contact plug 114d. 
Thereafter, as illustrated in FIG. 9L, the resist pattern 193 is removed. Subsequently, a barrier metal film (not-illustrated) is formed on the entire surface, and a tungsten film is formed thereon. Then, the tungsten film and the barrier metal film are polished until the NSG film 126 is exposed. As a result, contact plugs 129t are formed in the contact holes 127t, and contact plugs 129b are formed in the contact holes 127b. Further, contact plugs 129s are formed in the contact holes 128s, and a contact plug 129d is formed in the contact hole 128d. Next, plasma annealing is performed in a nitrogen atmosphere, and thereby the surface of the NSG film 126 is nitrided.
Next, as illustrated in FIG. 9M, wirings 130 in contact with the contact plugs 129t, 129b, 129s, and 129d are formed. Thereafter, a heat treatment is performed in a nitrogen atmosphere. Subsequently, an aluminum oxide film 131 is formed on the entire surface. Thereafter, upper layer wirings and so on are formed.
However, in the conventional method, as illustrated in FIG. 10A, after the resist pattern 193 is removed, substances 194 deteriorated from the resist pattern 193 are likely to be left in the contact holes 127t and 127b. This phenomenon is prominent in particular in the case when the aluminum oxide film 125 functioning as a hydrogen barrier film is formed above the ferroelectric capacitor. Therefore, as illustrated in FIG. 10B, the substances 194 are intervened between the contact plugs 129t and 129b and the top electrode and the bottom electrode, and contact resistances at these portions are likely to be increased. If ashing time and power for removing the resist pattern 193 are increased, it may possible to prevent the substances 194 from being left, but the ferroelectric capacitor C is affected.
Note that it can be considered that the contact plugs 129t and 129b are formed before the resist pattern 193 is formed, but in this case, plasma damage is likely to be caused to the ferroelectric capacitor C. Further, it is also difficult to recover this damage.
Further, it is also possible to consider that before the contact holes 127t and 127b are formed, the contact holes 128s and 128d and the contact plugs 129t and 129b are formed, but in this case, an oxidation preventing film for the contact plugs 129t and 129b, which is, for example, an aluminum oxide film, is required to be formed.
Therefore, the number of films whose etching rate is lower than that of a silicon oxide film is increased, and etching for forming the contact holes 127t and 127b becomes difficult to be performed. Then, lower portions of the contact holes 127t and 127b become too thin and/or variation in size of the contact holes 127t and 127b is likely to occur. Consequently, it is difficult to stabilize the characteristics such as the contact resistance.
Note that Patent Document 1 discloses an art in which after a conductive plug reaching a bottom electrode and a conductive plug reaching a semiconductor substrate are formed, a conductive plug reaching a top electrode is formed. However, in this art, a supply path for oxygen to a ferroelectric capacitor is not sufficient therefore being difficult to perform recovery annealing. Further, in forming an opening reaching the top electrode, there is a case that damage is caused to the ferroelectric capacitor via the conductive plug reaching the bottom electrode. Further, there are not many hydrogen barrier films, and therefore it is difficult to say that resistance to hydrogen diffusion is sufficient. Then, if the hydrogen barrier film is simply added to this art, there arises a new problem such as an increase of variation.
Patent Document 2 discloses an art in which after an opening reaching a top electrode is formed, an opening reaching a semiconductor substrate is formed. However, in this art, in forming the opening reaching the semiconductor substrate, significant damage is caused to a ferroelectric capacitor via the top electrode.
Patent Document 1: Japanese Laid-open Patent Publication No. 2002-9256
Patent Document 2: Japanese Laid-open Patent Publication No. 2000-164827
Patent Document 3: Japanese Patent No. 3165093